74HC259D/74HCT259D是8位可寻址锁存器

74HC259D/74HCT259D是8位可寻址锁存器介绍：

The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT259 are high-speed 8-bit addressable latches designed for general purpose storage applications in digital systems. The “259” are multifunctional devices capable of storing single-line data in eight addressable latches, and also 3-to-8 decoder and demultiplexer, with active HIGH outputs (Q0 to Q7), functions are available.

The “259” also incorporates an active LOW common reset (MR) for resetting all latches, as well as, an active LOW enable input (LE).

The “259” has four modes of operation as shown in the mode select table. In the addressable latch mode, data on the data line (D) is written into the addressed latch. The

addressed latch will follow the data input with all non-addressed latches remaining in their previous states.In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the D input with all other outputs in the LOW state. In the reset mode all outputs are LOW and unaffected by the address (A0 to A2) and data (D) input. When operating the “259” as an addressable latch, changing more than one bit of address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. The mode select table summarizes the operations of the “259”.

74HC259D/74HCT259D功能说明
· Combines demultiplexer and 8-bit latch
· Serial-to-parallel capability
· Output from each storage bit available
· Random (addressable) data entry
· Easily expandable
· Common reset input
· Useful as a 3-to-8 active HIGH decoder
· Output capability: standard
· ICC category: MSI

74HC259D/74HCT259D引脚管脚说明-PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3 A0 to A2 address inputs
4, 5, 6, 7, 9 10, 11, 12 Q0 to Q7 latch outputs
8 GND ground (0 V)
13 D data input
14 LE latch enable input (active LOW)
15 MR conditional reset input (active LOW)
16 VCC positive supply voltage

 74HC259D/74HCT259D逻辑图

更详细资料请查看：74HC259D

 

锁存器寻址HC259DHCT259Dspeed

免责声明：本网信息来自于互联网，目的在于传递更多信息，并不代表本网赞同其观点。其原创性以及文中陈述文字和内容未经本站证实，对本文以及其中全部或者部分内容、文字的真实性、完整性、及时性本站不作任何保证或承诺，并请自行核实相关内容。本站不承担此类作品侵权行为的直接责任及连带责任。如若本网有任何内容侵犯您的权益，请及时联系我们，本站将会在24小时内处理完毕。