首页 / 百科

MAX72420 背板和存储管理控制器

2010-09-22 00:00:00

MAX72420 背板和存储管理控制器

概述

The MAX72420 is a highly integrated management device intended to provide a cost-effective solution for baseboard, storage, or embedded system management. The device contains a high-performance, 32-bit RISC engine; a 10/100 Ethernet media-access controller (MAC); four master/slave mode I²C interfaces; a high-speed I²C master/slave core; two general-purpose universal asynchronous receiver-transmitters (UARTs); three 32-bit timers; up to 54 bits of general-purpose input/output (GPIO); 64KB of high-speed SRAM; an SPI™ memory interface; and an EJTAG port for firmware debug and development. The device optionally supports a configurable low-pin-count (LPC) system interface for applications requiring a direct system connection. The device also supports a connection to a network controller through a reduced media-independent interface (RMII), which can be configured as a network controller-sideband interface (NC-SI). The MAX72420, along with a minimum number of additional components, can be configured to support all management functions, while retaining the flexibility to support a significantly expanded system through various peripheral interfaces.

Because management functions typically require a limited amount of bandwidth and occur relatively infrequently, an embedded RISC engine operating over an SPI memory interface with zero-wait-state internal SRAM for critical code execution provides optimal performance with a low system cost. The MAX72420 also supports the next generation of SPI devices, which can double or quadruple the interface bandwidth by using additional signal pins. Several peripheral functions are included in the device to support a variety of embedded controller requirements. External component requirements are limited to a single SPI flash memory device and I²C peripherals dedicated to system management functions. Additional peripherals can be added through the GPIO interface.

The MAX72420 is available in an 88-ball, chip-scale ball-grid array (CSBGA) package.

关键特性

Integrated MX3 32-Bit RISC Microprocessor Core

Four Master/Slave Mode, Multimaster-Capable I²C Interfaces (IPMB)

High-Speed Master/Slave I²C Core

Up to 54 Bits of User-Definable General-Purpose I/O with Up to 42 External Interrupts

Master-Mode SPI Interface for Connection to Serial Flash ROM (Code Store) with Optional Dual/Quad SPI Support

Integrated 64KB Zero-Wait-State User Data SRAM

Three 32-Bit Programmable Timers, One Supports a Watchdog Timer

Two General-Purpose UARTs with Hardware Flow Control

10/100 Ethernet MAC for Connection to a Network Controller through an RMII or NC-SI

Integrated PLL for Use with a Low-Frequency/Low-Cost Crystal (Supports 4, 8, 10, or 12MHz Reference Clocks)

32 Optional Fan-Speed Monitor Inputs